In the field of cellular communication systems, communication devices, such as wireless telephone handsets, transmit and receive modulated Radio Frequency (RF) signals. For example, the Universal Mobile Telecommunications System (UMTS) system, developed by the 3rd Generation Partnership Project (3GPP) (www.3gpp.org), utilises Wideband Code Division Multiple Access (W-CDMA) modulation.
Upon receipt of such modulated RF signals, communication devices perform various amplification, filtering, mixing/conversion operations in order to extract wanted information from the received signals. For many applications, Very Low Intermediate Frequency (VLIF) receivers are used because the wanted down converted received signal that is digitised is not centred about DC (zero hertz). In this manner, DC offset removal can be performed in the digital domain without notching out centre channel power of the desired signal: a problem with Zero Intermediate Frequency (ZIF) receivers.
In many applications, the received signal is offset from DC so as to avoid 1/f noise (flicker noise) associated with signals about DC in the analogue domain. Furthermore, VLIF receivers also allow improved processing gain performance to interferers which manifest as IIP2 distortion, which is centred about DC. As will be known by a skilled artisan, IIP2 is a measure of the 2nd order intermodulation product of the receiver subsystem. For radio receivers, the most prevalent 2nd order distortion term is a result of self mixing interferer signals, the main resultant term for which is a DC component. Given the Time Division Multiple Access (TDMA) basis of many air interface protocols, this interferer may not be present during initialisation of the receiver circuits on a mobile radio communications device, and thus can not be calibrated out. Accordingly, the radio receiver must deal with abrupt changes to DC levels as pulsed interferers appear during reception. Furthermore as many modern air interface communication protocol use an Amplitude Modulation (AM) component, this AM term becomes centred on DC as a result of IIP2 distortion.
FIG. 1 illustrates an example of typical VLIF RF receiver circuitry 100 for such a communication device. Signals are received by an antenna 110. A transceiver switch 120 operably couples the antenna 110 to transceiver circuitry comprising a transmit chain 130 and a receive chain. During reception of a signal, the switch 120 isolates the antenna 110 from the transmit chain 130, and couples it to the receive chain. Typically for more recent receiver circuits, it is desirable for the processing of received signals to be performed in the digital domain, in order to improve the reliability of such processing. Accordingly, for the example illustrated in FIG. 1, the receive chain comprises digital processing circuitry 170. However, it is still necessary for some processing to be performed within the analogue domain. Accordingly, the receive chain further comprises a low noise amplifier LNA 140 for amplifying the received RF signal, a quadrature mixer 150 for producing In-phase (I) and Quadrature (Q) components of the received signal, and baseband filters 160. For the example illustrated in FIG. 1, the digital processing circuitry 170 is operably coupled to a baseband central processing unit (CPU) 180, and provides the information retrieved from the received signal thereto. However, in alternative examples, the digital processing circuitry 170 may form a part of the baseband CPU 180 integrated circuit device.
A problem encountered with processing received signals is that, as mentioned above, analogue signal processing inherently introduces DC offsets into a received signal. These digital offsets are then passed from the analogue domain on to the digital domain, and as a result have an effect on the received signal in a form of unwanted tones during the subsequent digital signal processing.
FIG. 2 illustrates an example of known digital signal processing circuitry 200, such as the digital processing circuitry 170 of FIG. 1. The digital signal processing circuitry 200 comprises, for each of the In-phase and Quadrature component paths, a Sigma-Delta analogue to digital converter (ADC) 210, and a down sampling sinc filter 215. The digital signal processing circuitry 200 also comprises amplitude IQ imbalance correction circuitry 220, image cancellation mixer circuitry 230, anti-alias filter (AAF) 235, downsampler 240, Channel selectivity filter 245 and digital RF interface 270 for providing an interface to, for example, the baseband DSP 180 in FIG. 1.
As previously mentioned, a problem encountered with processing received signals is that of the DC offsets introduced into the received signal during the analogue processing, and which are then passed on to the digital signal processing circuitry. As will be understood by a skilled artisan, any DC offset present within the signal during the image cancellation performed by the image cancellation mixer circuitry 230 will appear as tones at the intermediate frequency following the image cancellation, which cause interference with the wanted signal. As will also be appreciated by a skilled artisan, this is particularly problematic for very low intermediate frequency (VLIF) receivers.
The known solution illustrated in FIG. 2 for handling these DC offsets comprises, using a fine DC offset correction filter (high pass filter) 250 located in each of the In-phase and Quadrature component paths, before the signal reaches the IQ imbalance correction circuitry 220 and image cancellation mixer circuitry 230.
A problem with the use of such DC off set correction filters is that, because of their low bandwidths, they suffer from slow settling time responses. Consequently, the residual DC settling interferes with the wanted signal. If the bandwidth of the DC offset correction filter is increased in order to reduce the DC settling time, then this interferes with channel selectivity filtering within VLIF receivers. Consequently, the receiver circuitry is required to be switched on early, in the receiving and signal processing process in order to allow the DC filters time to settle. As a result, the receiver circuitry is required to be switched on for longer periods of time, and therefore increases the power consumption.
Furthermore, adjacent timeslot power levels will cause initial problematic sampled DC impulse. To those skilled in the art it will be appreciated that, while a radio receiver is enabled for reception, a DC offset calibration scheme may be invoked. While this calibration scheme is running, an adjacent time slot of transmission from the base station will be present on the air interface. This signal may have a very different power level to the one intended for the given receiver. This variation in power level may distort the DC offset calibration result of the receiver.
US Patent US20050009493(A1), “DC Offset correction for Very Low Intermediate Frequency Receivers” Yang et al. Jan. 13, 2005 (YANG), discloses a method of down converting an RF information signal to a baseband information signal is such a manner as to overcome the above mentioned problems experienced during DC offset removal within, for example, VLIF receivers. More particularly, this patent discloses two embodiments for removing the DC offset within a received signal. The first embodiment comprises digitising an entire received VLIF signal burst, and having digitised the entire signal burst, estimating the DC content of the entire burst. The DC estimate is then subtracted from the VLIF signal burst before down converting the signal from being VLIF centred to being DC centred. The second embodiment again comprises digitising an entire received VLIF signal. However, for the second embodiment, the estimation of the DC content, and the subtracting of the DC estimate from the received signal burst, is performed after down converting the signal from being VLIF centred to being DC centred.
However, a problem with each of the two embodiments disclosed in US20050009493 is that they both require the entire burst to be digitised before correcting the DC offset within the VLIF signal. Accordingly, it is not possible for the received signal to be processed in real time, since it inherently requires the received signal to be delayed whilst the entire signal burst is received, processed and used to estimate the DC content therefore. Only then may the DC content be removed, and the signal processed further. Such a delay in the processing of received signals is substantially incompatible with the increase in modem performance requirements.